Hello
can you develop an ARM application?
Is it possible?
thanks

No. Climate models are too complex for that.

Also, the models currently used are those created and used by the UK Met Office.
Oxford Uni doesn't create their own.

Hello
can you develop an ARM application?
Is it possible?
thanks

It is possible that the OpenIFS tasks might be able to run on risc chips. If not then new Macs will be in trouble.

Interesting though. My ARM device is running some flavour of Linux. Linux is Linux, what does the architecture of the CPU have to do with the matter?

The program uses one of the SSE instruction sets.
I forget now whether it's SSE2 or SSE4.

Interesting though. My ARM device is running some flavour of Linux. Linux is Linux, what does the architecture of the CPU have to do with the matter?

There are far too many design, implementation, programming and compiling variables to assume that the CPU architecture won't matter. The programs we are running were aimed at super-computers. Support for ARMv8-A in Linux is from around 2012. It's a long while since I used the first generation 6502 assembler. The original ARM was hard-wired, no Microcode (the Hardware Abstraction Layer) that translates the executable program into the chip's reduced instruction set. Even it ran an executable in Linux, these RISC chips are aimed at low power devices and will have (IIRC) an external L3 cache typically from 256KB to 4MB. Without architecture targeted programming/compilation, plus deep cache, don't expect data and cpu intensive programs (like CPDN) to behave nicely on a RISC device.

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Hello
can you develop an ARM application?
Is it possible?
thanks

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@fzs600. Go to World Community Grid. They need as many ARM devices( mobile devices, mobile phones, Single Board Computers) as possible for their COVID19 project. No lack of work either. Best of luck.

Interesting though. My ARM device is running some flavour of Linux. Linux is Linux, what does the architecture of the CPU have to do with the matter?

There are far too many design, implementation, programming and compiling variables to assume that the CPU architecture won't matter. The programs we are running were aimed at super-computers. Support for ARMv8-A in Linux is from around 2012. It's a long while since I used the first generation 6502 assembler. The original ARM was hard-wired, no Microcode (the Hardware Abstraction Layer) that translates the executable program into the chip's reduced instruction set. Even it ran an executable in Linux, these RISC chips are aimed at low power devices and will have (IIRC) an external L3 cache typically from 256KB to 4MB. Without architecture targeted programming/compilation, plus deep cache, don't expect data and cpu intensive programs (like CPDN) to behave nicely on a RISC device.

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The cache problem I can understand, only now they have started to increase the cache size but still nowhere near the required amount.
Les, the instruction sets SSE2 and SSE4 are in Linux. The others also, that is why we are running WU's in Linux on x86 and x64.

The program uses one of the SSE instruction sets.
I forget now whether it's SSE2 or SSE4.

I remember when this came in and older CPU's that didn't support SSE2 became obsolete as far as CPDN is concerned. Not sure whether SSE4 is a requirement now or not. Linux or other OS having SSE2/4 may be needed but the CPU needs to support the instruction set as well.

The program uses one of the SSE instruction sets.
I forget now whether it's SSE2 or SSE4.

I remember when this came in and older CPU's that didn't support SSE2 became obsolete as far as CPDN is concerned. Not sure whether SSE4 is a requirement now or not. Linux or other OS having SSE2/4 may be needed but the CPU needs to support the instruction set as well.

SSE2 was first supported around 2000 on Pentium devices as part of INTEL proprietary IA-32 architecture, a step beyond the late-1990's INTEL MMX instruction set. AMD provided an emulation of IA-32 instructions on Athlon devices. SSE2 was (IIRC) was the limit to use INTEL P4 and AMD Athlon devices for early CPDN contributors. IIRC the SSE2 instruction set (or emulation by the Hardware Abstraction Layer) of the target CPU is essential for CPDN.

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With original cpdn and the initial boinc cpdn, not even SSE was needed as a Pentium II could run it. I can't remember when it happened but then the base became SSE sometime between 2004 and 2006. And then in 2009, new executables were compiled that required SSE2. I don't believe that any further CPU requirements exist for the wah2 or hadam type models beyond SSE2 and intel/amd x86/x86_64 type CPUs.

Just came across this thread. OpenIFS has been successfully compiled and run on an ARM device. If you look at the list of applications on the CPDN pages you'll see it listed. It did not run particularly fast but that's fairly normal for porting a big model code to a new processor. I don't believe there are any plans to do much more with it.